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    出版年份著作著作人
    1993Pei-Yung Hsiao, Chiao-Yi Lin, and Shew Paul Waie, "OTP: An Optimal Tile Partition for the Space Region of Integrated Circuits Geometry" , IEE Proceedings-E Computers and Digital Techniques , 140 , 3 , 1993, pp145-153 (SCI)蕭培墉
    1992Pei-Yung Hsiao and Jin-Tai Yan, "Designing a Complementary Design Rule Checker Based on Binary Balanced Quad List Quad Tree" , IEE Proceedings-E Computers and Digital Techniques , 139 , 4 , 1992, pp311-322 (SCI)蕭培墉
    1991Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, and Wu-Shiung Feng, "A Knowledge-Based Program for Compacting Mask Layout of Integrated Circuits" , Int. J. of Computer-Aided Design , 23 , 3 , 1991, pp223-231 (SCI)蕭培墉
    1991Chia-Chiung Tsai, S. J. Chen, Pei-Yung Hsiao, and Wu-Shiung Feng, "Routing Area Compaction Based on Iterative Construction" , Journal of the Chinese Inst. of Engineers , 14 , 3 , 1991, pp239-256 (SCI)蕭培墉
    1991Chia-Chun Tsai, S. J. Chen, Pei-Yung Hsiao, and Wu-Shiung Feng, "A New Iterative Construction Approach to Routing With Compacted Area" , IEE Proceedings-E Computers and Digital Techniques , 138 , 1 , 1991, pp57-71 (SCI)蕭培墉
    1991Pei-Yung Hsiao and Chia-Chun Tsai, "Expert Compactor: a Knowledge-Based Application in VLSI Layout Compaction" , IEE Proceedings-E Computers and Digital Techniques , 138 , 1 , 1991, pp13-20 (SCI)蕭培墉
    1990Pei-Yung Hsiao and Wu-Shiung Feng, "Using Multiple Storage Quad Tree on a Hierarchical VLSI Compaction Scheme" , IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems , 9 , 5 , 1990, pp522-536 (SCI)蕭培墉
    1990Pei-Yung Hsiao and Wu-Shiung Feng, "New Algorithms Based on Multiple Storage Quadtrees in Hierarchical Compaction of VLSI Mask Layout" , Int. J. of Computer-Aided Design , 22 , 2 , 1990, pp74-80 (SCI)蕭培墉
    1990Pei-Yung Hsiao, S. F. Steven Chen, and Wu-Shiung Feng, "A New Control Strategy for An A.I. Approach to VLSI Layout Compaction" , INTEGERATION, the VLSI journal , 10 , 1 , 1990, pp55-70 (SCI)蕭培墉
    1989Pei-Yung Hsiao, Wu-Shiung Feng and S. F. Steven Chen, "An Application of Expert System in Layout Compaction of VLSI Design" , Journal of the Chinese Inst. of Engineers , 12 , 4 , 1989, pp497-510 (SCI)蕭培墉

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