友善列印 - Chiang Te-Kuang, ”Elliptical Nanowire FET: Modeling the Short-Channel Subthreshold Current Caused by Interface-trapped-Charge and Its Evaluation for Subthreshold Logic Gate” Superlattices and microstructures, Vol.6, No.4, pp.1083-1092, 2020.

Chiang Te-Kuang, ”Elliptical Nanowire FET: Modeling the Short-Channel Subthreshold Current Caused by Interface-trapped-Charge and Its Evaluation for Subthreshold Logic Gate” Superlattices and microstructures, Vol.6, No.4, pp.1083-1092, 2020.

出版日期：2019-08-01

期刊等級：SCI

論文名稱(篇名)：AElliptical Nanowire FET: Modeling the Short-Channel Subthreshold Current Caused by Interface-trapped-Charge and Its Evaluation for Subthreshold Logic Gate

期刊名： Superlattices and microstructures

卷數：6

期數：4

起頁：1083

迄頁：1092

作者中文名：江德光

作者英文名：Te-Kung Chiang

全部作者：Te-Kuang Chiang

著作人數：1

作者型態：Corresponding Author

使用語言：英文