計畫名稱：D頻帶可調式濾波型功率分配/結合器設計
執行起迄：2019/08/01~2020/10/31
總核定金額：844,000元
計畫概述：本計畫擬發展D頻帶晶片層級之濾波型功率分配器，將應用在總計畫環境偵測雷達系統，亦可用於其他感測與成像、無線通訊等系統，開發成果的專利與技術轉移亦將對於國內廠商的高頻電路技術發展有所助益。此外，透過計畫之進行，將培育毫米波頻段晶片電路設計人才，而對於透過整合計畫之合作，亦將加強國內大專院校間的師生團隊合作與技術發展。
中文摘要：本研究計畫採用TSMC 90-nm 1P9M 厚金屬CMOS製程，設計兩個D頻帶具頻率可調特性的濾波型功率分配器。其中一個功率分配器，命名為設計I，由雙模開環路共振腔組成。另一個功率分配器，命名為設計II，由四分之一波長共振腔搭配網狀彎折佈局所組成。共振腔接上P/N 接面變電容來產生頻率可調性。模擬結果顯示，設計I的濾波型功率分配器在偏壓 0 – 2 V的變化內，其操作頻率可由164.5 GHz 改變到175.0 GHz，而設計II的濾波型功率分配器在偏壓 0 – 1 V的變化內，其操作頻率可由156.6 GHz 改變到165.7 GHz。兩功率分配器的植入損失分別為3+10.0 – 3+7.7 dB 和3+15.4 – 3+13.1 dB，其中3-dB的植入損失來自功率分配。設計I的濾波型功率分配器包含量測墊所占的電路佈局面積為991.0 um × 261.6 um，在中心頻率170 GHz 的電氣尺寸為0.562 波長 × 0.148 波長。設計I的濾波型功率分配器包含量測墊所占的電路佈局面積為740.5 um × 420.2 um，在中心頻率160 GHz 的電氣尺寸為0.420 波長 × 0.238 波長。 我們在前一期計畫(MOST 107-2221-E-390-005-)採用TSMC 0.18-um CMOS製程設計了四個濾波型功率分配器，其中三個電路已經製作完成但報告繳交當時尚未量測。這三個濾波型功率分配器的量測結果將在附錄A呈現，並與模擬結果做比較。
英文摘要：Two D-band tunable filtering power dividers using TSMC 90-nm 1P9M ultra-thick top metal CMOS technology are designed in this project. One of the power dividers which is named type-I design consists of dual-mode open-loop resonators, and the other which is named type-II design consists of net-type quarter-wavelength resonators. The resonators are connected with junction varactors for frequency tunability. Simulated results show that type-I filtering power divider has an operating frequency of 164.5 GHz – 175.0 GHz for 0 – 2 V tuning voltage, and type-II filtering power divider has an operating frequency of 156.6 GHz – 165.7 GHz for 0 – 1 V tuning voltage. The insertion loss of these power dividers ranges from 3+10.0 dB to 3+7.7 dB and from 3+15.4 to 3+13.1 dB, respectively, where 3-dB insertion loss originates from power division. The layout of type-I filtering power divider with pads occupies an area of 991.0 um × 261.6 um which is 0.562 wavelength × 0.148 wavelength at the center frequency of 170 GHz. The layout of type-II filtering power divider with pads occupies an area of 740.5 um × 420.2 um which is 0.420 wavelength × 0.238 wavelength at the center frequency of 160 GHz. In our previous project (MOST 107-2221-E-390-005-), four filtering power dividers have been designed with TSMC 0.18-um CMOS technology. Three of them have been fabricated but not measured when the project report was submitted. In Appendix A, measured results of these filtering power dividers are presented and compared with simulated data.