計畫名稱：非接觸測量技術應用於系統電路信號整合分析技術研究
執行起迄：2018/08/01~2019/07/31
總核定金額：700,000元
中文摘要：整合雙面直接針測及近場量測測試技術，發展系統電路層級之靜電放電路徑檢測與解決方案、系統電路同步切換雜訊頻域暨時域產生機制檢測應用，建立系統電路層級在靜電防護與高速同步切換雜訊上最佳化設計與解決方案。主要之研究項目有： 1.藉由使用近場環境建立之系統電路層級靜電消散路徑量測技術，驗證系統構裝及系統電路之靜電消散機制及路徑，藉由改善電路設計及消散路徑重整以降低或避免靜電對於晶片之衝擊損害，提升系統電路靜電放電損傷承受力。目標在於電路板系統設計對於ESD耐受影響及最佳化，如：不同電源分布網路設計、磁珠(Bead)之作用與影響、訊號線路設計影響等，以發展傳導雜訊傳遞路徑檢測技術，建立系統電路訊號與電源整合量測技術。 2.時域與頻域同步切換雜訊量測機制建立後，實際系統電路不同設計時同步切換雜訊產生頻率之掃頻測試，及切換雜訊在產生頻率上之時間波動變化，並整合如：解耦合電容(Decoupling Capacitor)之解決方案，建立抑制機制與最佳化方案提供。
英文摘要：In this project, two major study items for Signal and Power Integrity are proposed depend on near field measurement technology and direct double-side probing measurement. Analysis solutions of Time-varying ESD dissipation path and simultaneous switch noise are proposed in this project for SiP and System circuit. Including: 1. Test and Simulation Architecture for Electrostatic Discharge Path Measurement by Near-field measurement technology will be developed. Optimize the ability of the SiP circuit to design the static dissipation capability, then, the design criteria and solutions of the ESD system are proposed. 2. Establishment of testing and simulation architecture of High-speed digital circuit simultaneous switching noise. Design guidelines and solutions for optimization of signal integrity and power supply integration performance of System in package. Then, provide current solution optimization and new solutions proposed.