友善列印 - Pei-Yung Hsiao and Lih-Der Jang, "Using a Balanced Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme," IEEE 5th International Conf. on VLSI Design, Bangalore, India, pp.370-371, Jan. 1992. (EI)

電機工程學系

Pei-Yung Hsiao and Lih-Der Jang, "Using a Balanced Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme," IEEE 5th International Conf. on VLSI Design, Bangalore, India, pp.370-371, Jan. 1992. (EI)