友善列印 - Pei-Yung Hsiao, Chun-Ho Hua, and Chien-Chen Lin, “A Novel FPGA Architectural Implementation of Pipelined Thinning Algorithm,” IEEE Int’l Symp. on Circuits and Systems, Vancouver, Canada, May 23-26, 2004(EI)

電機工程學系

Pei-Yung Hsiao, Chun-Ho Hua, and Chien-Chen Lin, “A Novel FPGA Architectural Implementation of Pipelined Thinning Algorithm,” IEEE Int’l Symp. on Circuits and Systems, Vancouver, Canada, May 23-26, 2004(EI)