105學年度：超薄式全空乏、塊狀基板與絕緣層覆矽鳍式電晶體效能與可靠度比較
計畫名稱：超薄式全空乏、塊狀基板與絕緣層覆矽鳍式電晶體效能與可靠度比較
執行起迄：2016/08/01~2017/07/31
總核定金額：715,000元
中文摘要：鰭式電晶體( FinFET)和超薄絕緣體上矽全空乏電晶體(UTBB-FDSOI)是目前先進積體電路中，最主要使用的電晶體。藉由基體電壓的改變有助於調整電晶體的臨界電壓，並使IC設計人員能夠實現高效率和低功耗的操作。本研究藉基體電壓來比較UTBB-FDSOI、塊狀基板電晶體(Bulk FinFET) 和絕緣層覆矽鳍式電晶體(SOI FinFET)，其絕緣體厚度> 150nm)的電特性，並以熱載子注入應力(Hot carrier stress；HCS)，觀察期衰退變化。基於基體偏壓對電特性的影響，提出了基體電壓阻抗模型。基體電壓的HCS在可靠性測試期間顯示對UTBB FDSOI 的影響遠大於 bulk FinFET。比較時間對HCS 電壓之斜率，FinFET顯示出比UTBB FDSOI 尺寸縮減下，更快的衰減速度。合理的可用多閘極帶來較高的閘極-通道之電場增加來解釋。
英文摘要：FinFETs and ultra-thin body and buried oxide fully depleted silicon on insulator (UTBB-FDSOI) are the main transistors currently used in advanced integrated circuits (ICs). The tunable electrical properties via back-biasing facilitate the threshold voltage adjustment and enable IC designers to achieve a highly efficient and low-power-consuming operation. This study compares the modulation rate before and after hot carrier stress (HCS) of bulk FinFETs, UTBB-FDSOI (tBOX=20 nm), and SOI FinFETs (tBOX>150 nm) via back-biasing. Simplified back-impedance models are proposed based on the impact of back-biasing on electrical characterization. Additionally, HCS with back-biasing shows a higher impact on UTBB FDSOI than on bulk FinFETs during reliability test, implying that the tBOX plays a critical role in the modulation rate. The lifetime with HCS indicates that the bulk FinFETs exhibits faster downscaling degradation than UTBB FDSOI probably due to the nature of multi-gate devices whose vertical electrical field should increase faster than planer devices during scaling.
執行起迄：2016/08/01~2017/07/31
總核定金額：715,000元
中文摘要：鰭式電晶體( FinFET)和超薄絕緣體上矽全空乏電晶體(UTBB-FDSOI)是目前先進積體電路中，最主要使用的電晶體。藉由基體電壓的改變有助於調整電晶體的臨界電壓，並使IC設計人員能夠實現高效率和低功耗的操作。本研究藉基體電壓來比較UTBB-FDSOI、塊狀基板電晶體(Bulk FinFET) 和絕緣層覆矽鳍式電晶體(SOI FinFET)，其絕緣體厚度> 150nm)的電特性，並以熱載子注入應力(Hot carrier stress；HCS)，觀察期衰退變化。基於基體偏壓對電特性的影響，提出了基體電壓阻抗模型。基體電壓的HCS在可靠性測試期間顯示對UTBB FDSOI 的影響遠大於 bulk FinFET。比較時間對HCS 電壓之斜率，FinFET顯示出比UTBB FDSOI 尺寸縮減下，更快的衰減速度。合理的可用多閘極帶來較高的閘極-通道之電場增加來解釋。
英文摘要：FinFETs and ultra-thin body and buried oxide fully depleted silicon on insulator (UTBB-FDSOI) are the main transistors currently used in advanced integrated circuits (ICs). The tunable electrical properties via back-biasing facilitate the threshold voltage adjustment and enable IC designers to achieve a highly efficient and low-power-consuming operation. This study compares the modulation rate before and after hot carrier stress (HCS) of bulk FinFETs, UTBB-FDSOI (tBOX=20 nm), and SOI FinFETs (tBOX>150 nm) via back-biasing. Simplified back-impedance models are proposed based on the impact of back-biasing on electrical characterization. Additionally, HCS with back-biasing shows a higher impact on UTBB FDSOI than on bulk FinFETs during reliability test, implying that the tBOX plays a critical role in the modulation rate. The lifetime with HCS indicates that the bulk FinFETs exhibits faster downscaling degradation than UTBB FDSOI probably due to the nature of multi-gate devices whose vertical electrical field should increase faster than planer devices during scaling.
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