104學年度：最新准三維四重閘極穿透式場效電晶體之解析模型
計畫名稱：最新准三維四重閘極穿透式場效電晶體之解析模型
執行起迄：2015/08/01~2016/09/30
總核定金額：546,000元
中文摘要：簡介 吾人利用周長加權法之概念，推導出一新型之四重閘極穿透式場效電晶體之解析模型，此理論避開繁雜之數學運算，提供快速且有效之短通道行為含臨界電壓與汲極電流分析方法，此理論可以適用於任何之多閘極穿透式電晶體之短通道效應之分析。基於此新型之四重閘極穿透式場效電晶體之解析模型，吾人可以輕易求得自然長度/微縮長度，利用此自然長度/微縮長度，吾人可以求得最小之中心電壓，進而以此最小電位為條件，配合穿透理論，應用於求出四重閘極穿透式場效電晶體之臨界電壓與汲極電流。總而言之，本研究計劃藉由周長加權法推導出有『四重閘極穿透式效電晶體之新型最小中心電位』，再應用此新型最小中心電位配合電子穿透理論推導出有關『四重閘極穿透式電晶體之解析行為含臨界電壓與汲極電流』之解析模型。此計畫之研究成果可以提供未來『四重閘極穿透式場效電晶體』當其應用於記憶體電路有效之評估公式
英文摘要：Due to the very low leakage current, the inter-band tunneling field-effect transistor (TFET) outweighs the conventional MOSFET in saving power consumption and emerges as a potential candidate for the low-power applications. On the other hand, the non-planar MOSFETs (i.e., multiple-gate (MG) MOSFETs) such as double-gate (DG), surrounding-gate (SRG), and quadruple-gate (QG) MOSFETs have been shown to be suitable for the nanometer scaling because they provide better immunity to SCEs than the conventional planar MOSFETs. By incorporating MG with TFET device structures, the MG-TEFTs such as DG-TFET, SRG-TFET, and QG-TFET should be the promising devices for the nanometer scaling and low power ULSI circuit application. Recently, the analytical models for both the DG-TFET and SRG-TFET have been developed based on the 2-D and quasi-2-D potential approaches. So far, there is no work focused on the QG-TEFT modeling. It is known that DG-TEFT and SRG-TFET have the 2-D symmetrical structure in the bulk silicon, which causes the 2-D analytical solutions to be sufficient to derive the device model. However, the QG-TFET device inherits the 3-D structure in the bulk silicon, which makes the 2-D analytical approach fail to model the device. Instead of using 2-D analytical approach, the 3-D solution method is an alternative approach to develop the device model. However; the 3-D solution approach involves so much mathematics that overshadows the device physics and makes it impractical to be used in the real circuit application. To make use of QG-TFET in the circuit application, it is mandatory to develop a feasible device model. In this project, based on the Perimeter-Weighted-Sum Method (PWSM) together with the Equivalent Number of Gates (ENG), we present a novel quasi-3-D analytical model for the QG-TEFT, which includes the quasi-3-D potential, threshold voltage, and tunneling current. The model eliminates the complicated mathematics involved in 3-D analytical solution. Besides giving a physical insight into the device physics, the developed model is very useful in the circuit simulation due to its computational efficiency and feasible formula.
執行起迄：2015/08/01~2016/09/30
總核定金額：546,000元
中文摘要：簡介 吾人利用周長加權法之概念，推導出一新型之四重閘極穿透式場效電晶體之解析模型，此理論避開繁雜之數學運算，提供快速且有效之短通道行為含臨界電壓與汲極電流分析方法，此理論可以適用於任何之多閘極穿透式電晶體之短通道效應之分析。基於此新型之四重閘極穿透式場效電晶體之解析模型，吾人可以輕易求得自然長度/微縮長度，利用此自然長度/微縮長度，吾人可以求得最小之中心電壓，進而以此最小電位為條件，配合穿透理論，應用於求出四重閘極穿透式場效電晶體之臨界電壓與汲極電流。總而言之，本研究計劃藉由周長加權法推導出有『四重閘極穿透式效電晶體之新型最小中心電位』，再應用此新型最小中心電位配合電子穿透理論推導出有關『四重閘極穿透式電晶體之解析行為含臨界電壓與汲極電流』之解析模型。此計畫之研究成果可以提供未來『四重閘極穿透式場效電晶體』當其應用於記憶體電路有效之評估公式
英文摘要：Due to the very low leakage current, the inter-band tunneling field-effect transistor (TFET) outweighs the conventional MOSFET in saving power consumption and emerges as a potential candidate for the low-power applications. On the other hand, the non-planar MOSFETs (i.e., multiple-gate (MG) MOSFETs) such as double-gate (DG), surrounding-gate (SRG), and quadruple-gate (QG) MOSFETs have been shown to be suitable for the nanometer scaling because they provide better immunity to SCEs than the conventional planar MOSFETs. By incorporating MG with TFET device structures, the MG-TEFTs such as DG-TFET, SRG-TFET, and QG-TFET should be the promising devices for the nanometer scaling and low power ULSI circuit application. Recently, the analytical models for both the DG-TFET and SRG-TFET have been developed based on the 2-D and quasi-2-D potential approaches. So far, there is no work focused on the QG-TEFT modeling. It is known that DG-TEFT and SRG-TFET have the 2-D symmetrical structure in the bulk silicon, which causes the 2-D analytical solutions to be sufficient to derive the device model. However, the QG-TFET device inherits the 3-D structure in the bulk silicon, which makes the 2-D analytical approach fail to model the device. Instead of using 2-D analytical approach, the 3-D solution method is an alternative approach to develop the device model. However; the 3-D solution approach involves so much mathematics that overshadows the device physics and makes it impractical to be used in the real circuit application. To make use of QG-TFET in the circuit application, it is mandatory to develop a feasible device model. In this project, based on the Perimeter-Weighted-Sum Method (PWSM) together with the Equivalent Number of Gates (ENG), we present a novel quasi-3-D analytical model for the QG-TEFT, which includes the quasi-3-D potential, threshold voltage, and tunneling current. The model eliminates the complicated mathematics involved in 3-D analytical solution. Besides giving a physical insight into the device physics, the developed model is very useful in the circuit simulation due to its computational efficiency and feasible formula.
Click Num: