103學年度：可程序規劃密碼系統之可測試性設計
計畫名稱：可程序規劃密碼系統之可測試性設計
執行起迄：2014/08/01~2015/10/31
總核定金額：600,000元
中文摘要：本計畫提出了幾個測試再利用的機制於加解密系統晶片中，使矽智產更易於被測試。以IEEE Std. 1500的邊界掃描架構來測試系統晶片的矽智產。而IEEE Std. 1500的序列測試機制在測試大量測試試樣時需花費較多時間，於是將BIST與邊界掃描架構整合於一起，來縮減測試上的時間，並於待測電路植入內部掃描鏈來增加測試覆蓋率。 另一個測試機制為Avalon bus Test Interface Controller，以外部測試匯流排來控制該測試機制，透過系統匯流排來對系統上的模組讀寫，讓使用者了解系統內部的行為。而整體驗證的流程以自動化驗證機制來做管理，來減少重覆測試時間上的冗長
英文摘要：This project proposes several test reuse mechanisms in a Cryptographic SoC to let the hardware modules (IP) be easier to be tested. The IEEE Std. 1500 uses boundary scan structure to test the IP. It need to spend more time when using IEEE Std. 1500 serial testing mechanism to apply a large amount of test patterns. To reduce the test time, we integrate the BIST technique with the boundary scan structure. In addition, we insert the internal scan chains in the DUT to increase the fault coverage. Another testing mechanism in this project is the Avalon bus Test Interface Controller. It is controlled by the external test bus, and through the system bus to read and write the system component. It allows user to understand the behavior of the internal system. The overall verification process is managed by automatic verification mechanism, to reduce the test time.
執行起迄：2014/08/01~2015/10/31
總核定金額：600,000元
中文摘要：本計畫提出了幾個測試再利用的機制於加解密系統晶片中，使矽智產更易於被測試。以IEEE Std. 1500的邊界掃描架構來測試系統晶片的矽智產。而IEEE Std. 1500的序列測試機制在測試大量測試試樣時需花費較多時間，於是將BIST與邊界掃描架構整合於一起，來縮減測試上的時間，並於待測電路植入內部掃描鏈來增加測試覆蓋率。 另一個測試機制為Avalon bus Test Interface Controller，以外部測試匯流排來控制該測試機制，透過系統匯流排來對系統上的模組讀寫，讓使用者了解系統內部的行為。而整體驗證的流程以自動化驗證機制來做管理，來減少重覆測試時間上的冗長
英文摘要：This project proposes several test reuse mechanisms in a Cryptographic SoC to let the hardware modules (IP) be easier to be tested. The IEEE Std. 1500 uses boundary scan structure to test the IP. It need to spend more time when using IEEE Std. 1500 serial testing mechanism to apply a large amount of test patterns. To reduce the test time, we integrate the BIST technique with the boundary scan structure. In addition, we insert the internal scan chains in the DUT to increase the fault coverage. Another testing mechanism in this project is the Avalon bus Test Interface Controller. It is controlled by the external test bus, and through the system bus to read and write the system component. It allows user to understand the behavior of the internal system. The overall verification process is managed by automatic verification mechanism, to reduce the test time.
Click Num: