100學年度：可程序規劃之多核心密碼系統
計畫名稱：可程序規劃之多核心密碼系統
執行起迄：2011/08/01~2012/10/31
總核定金額：648,000元
中文摘要：近年來IC 科技發展非常迅速，科技的進步帶來通訊上的便利，也因此資訊安全的重要性日益提升，例如TPM (Trusted Platform Module) 電腦硬體防護技術與VPN (Virtual Private Network) 的網路安全防護技術等，這些都是針對密碼技術的研究，是目前備受到重視的課題。所以在本計畫，我們著力於加解密系統晶片的開發與整合。 在一個健全的密碼系統晶片上，應該有能力抵禦到各種安全性的攻擊。將密碼學中的私密金鑰演算法與公開金鑰演算法整合，可以全面性達到安全防護的效能。並加入亂數產生器的應用，可使得密碼系統的安全強度提升；另外，考量應用在嵌入式產品上的功率消耗限制，本計畫提出一電源管理控制器，成功整合Clock Gating 與Multiple Frequency Technology 兩種技巧；在軟體發展上，論文使用NIOS II IDE 軟體發展工具，配合CSoPC Prototype Verification 驗證介面，將運算資料與控制指令傳送至NIOS II-based 的SOPC 系統內，驗證系統運算結果。本計畫針對嵌入式產品的應用，成功提出一個低功率消耗密碼系統晶片。
英文摘要：Recently, the IC technology develops very rapidly. The progress of the technology makes the communication convenient, so the security of information becomes more and more important. There are many skills which are relative to the security of information, such as TPM (Trusted Platform Module) and VPN (Virtual Private Network). The development of security technique is an important issue. In this project, we focus on the development and integration of a Cryptosystem SoC. A robust Cryptosystem SoC should be able to resist the attacks of the security information. It should integrate the private-key algorithm with public-key algorithm to fully protect the security information. Furthermore, it should provide the random number generator to promote the security level. Due to the limited power consumption on embedded system products, this project proposes a power management controller that integrates the technologies of Clock Gating and Multiple Frequency Technology. On the software development, this project uses the NIOS II IDE software development tool and CSoPC Prototype Verification interface to transmit the operating data and controlling commands to the NIOS II-based SOPC system and verify the operation results. We focus on the application of embedded products and succeed in developing a low-power cryptosystem SoC.
執行起迄：2011/08/01~2012/10/31
總核定金額：648,000元
中文摘要：近年來IC 科技發展非常迅速，科技的進步帶來通訊上的便利，也因此資訊安全的重要性日益提升，例如TPM (Trusted Platform Module) 電腦硬體防護技術與VPN (Virtual Private Network) 的網路安全防護技術等，這些都是針對密碼技術的研究，是目前備受到重視的課題。所以在本計畫，我們著力於加解密系統晶片的開發與整合。 在一個健全的密碼系統晶片上，應該有能力抵禦到各種安全性的攻擊。將密碼學中的私密金鑰演算法與公開金鑰演算法整合，可以全面性達到安全防護的效能。並加入亂數產生器的應用，可使得密碼系統的安全強度提升；另外，考量應用在嵌入式產品上的功率消耗限制，本計畫提出一電源管理控制器，成功整合Clock Gating 與Multiple Frequency Technology 兩種技巧；在軟體發展上，論文使用NIOS II IDE 軟體發展工具，配合CSoPC Prototype Verification 驗證介面，將運算資料與控制指令傳送至NIOS II-based 的SOPC 系統內，驗證系統運算結果。本計畫針對嵌入式產品的應用，成功提出一個低功率消耗密碼系統晶片。
英文摘要：Recently, the IC technology develops very rapidly. The progress of the technology makes the communication convenient, so the security of information becomes more and more important. There are many skills which are relative to the security of information, such as TPM (Trusted Platform Module) and VPN (Virtual Private Network). The development of security technique is an important issue. In this project, we focus on the development and integration of a Cryptosystem SoC. A robust Cryptosystem SoC should be able to resist the attacks of the security information. It should integrate the private-key algorithm with public-key algorithm to fully protect the security information. Furthermore, it should provide the random number generator to promote the security level. Due to the limited power consumption on embedded system products, this project proposes a power management controller that integrates the technologies of Clock Gating and Multiple Frequency Technology. On the software development, this project uses the NIOS II IDE software development tool and CSoPC Prototype Verification interface to transmit the operating data and controlling commands to the NIOS II-based SOPC system and verify the operation results. We focus on the application of embedded products and succeed in developing a low-power cryptosystem SoC.
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