103學年度：以主動電路晶片進行之構裝電磁干擾與電源訊號整合分析研究
計畫名稱：以主動電路晶片進行之構裝電磁干擾與電源訊號整合分析研究
執行起迄：2014/08/01~2016/07/31
總核定金額：1,542,000元
中文摘要：隨著晶片製程技術朝向高頻、高速和低功率發展，系統對電壓雜訊耐受度逐漸降低，以往針對PCB載板加入電容進行優化，造成不必要成本的浪費。以封裝設計者角度，針對此因素設計球狀陣列封裝(Ball Grid Array, BGA)基板，固定接地系統，設計不同電源路徑，於基板上方承載主動晶片-反相器，進行電源配送網路(Power Delivery Network, PDN) 分析。討論晶片與構裝基板之間干擾，提出電源配送網路設計準則(PDN Design Rules)以取得最佳化設計。 當中主要之研究分析在於BGA構裝基板有無電源環(Power Ring)、不同打線圖(Bonding Diagram, BD)、不同電源球(Power Balls)及接地球(Ground Balls)之擺放設計，及不同訊號路徑設計等因素，選用最佳和最差PDN設計，探討構裝系統和晶片之間電源完整性(Power Integrity)及訊號完整性(Signal Integrity)。最後，利用晶片經過不同路徑訊號輸出，驗證微電子構裝實驗室封裝設計模組(Package IP)。
英文摘要：The system voltage noise tolerance decreases in wafer process technology by high frequency, high-speed and low-power development. In the past, adding cost of waste capacitors to optimize in PCB. In this paper, design the Ball Grid Array substrates by package designer. The ground system is fixed to the different power paths. The power delivery network analyses of the Inverter on the chip. The characteristics of the interference between chips and package, the best power paths by system design guides. In this paper, the power effects of Ball Grid Array are analyzed by changing the without power ring, bonding diagram, power /ground balls and the different signal paths. Using the best and worst sample to analyze power integrity and signal integrity. Finally, the Package IP is set up to test the different signal paths of the chip.
執行起迄：2014/08/01~2016/07/31
總核定金額：1,542,000元
中文摘要：隨著晶片製程技術朝向高頻、高速和低功率發展，系統對電壓雜訊耐受度逐漸降低，以往針對PCB載板加入電容進行優化，造成不必要成本的浪費。以封裝設計者角度，針對此因素設計球狀陣列封裝(Ball Grid Array, BGA)基板，固定接地系統，設計不同電源路徑，於基板上方承載主動晶片-反相器，進行電源配送網路(Power Delivery Network, PDN) 分析。討論晶片與構裝基板之間干擾，提出電源配送網路設計準則(PDN Design Rules)以取得最佳化設計。 當中主要之研究分析在於BGA構裝基板有無電源環(Power Ring)、不同打線圖(Bonding Diagram, BD)、不同電源球(Power Balls)及接地球(Ground Balls)之擺放設計，及不同訊號路徑設計等因素，選用最佳和最差PDN設計，探討構裝系統和晶片之間電源完整性(Power Integrity)及訊號完整性(Signal Integrity)。最後，利用晶片經過不同路徑訊號輸出，驗證微電子構裝實驗室封裝設計模組(Package IP)。
英文摘要：The system voltage noise tolerance decreases in wafer process technology by high frequency, high-speed and low-power development. In the past, adding cost of waste capacitors to optimize in PCB. In this paper, design the Ball Grid Array substrates by package designer. The ground system is fixed to the different power paths. The power delivery network analyses of the Inverter on the chip. The characteristics of the interference between chips and package, the best power paths by system design guides. In this paper, the power effects of Ball Grid Array are analyzed by changing the without power ring, bonding diagram, power /ground balls and the different signal paths. Using the best and worst sample to analyze power integrity and signal integrity. Finally, the Package IP is set up to test the different signal paths of the chip.
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